testing - VHDL testbench real-life example -

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I think I have read most textbooks which dedicate chapters, sections or whole texts to write testbench in VHDL . Still, I have the impression that none of them is showing the real thing seriously, if everything happens to write testbanks, then the complete verification process looks a little lower for me.

Is there any real life, high quality, industry-level testbank VHDL code which is open for study?

PS: I just finished reading writing testbench - function verification of HDL model , and although this is a great book, I still want to see some real life in the book Code example based on the proposed method


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